1. Field of the Invention
The present invention relates to a capacitor built-in interposer and a method of manufacturing the same and an electronic component device and, more particularly, a capacitor built-in interposer applicable to an interposer used to connect a semiconductor chip and a wiring substrate and a method of manufacturing the same and an electronic component device utilizing the same.
2. Description of the Related Art
In the prior art, there is the electronic component device constructed by mounting the semiconductor chip on the wiring substrate in which the decoupling capacitor is built. As shown in FIG. 1, in an example of such electronic component device, first wiring layers 100 are embedded in a first interlayer insulating layer 200 in a state that their lower surfaces are exposed, and second wiring layers 120 connected to the first wiring layers 100 via first via holes VH1 provided in the first interlayer insulating layer 200 are formed on the first interlayer insulating layer 200.
Also, connection terminals 340 of a capacitor component 300 constructed by forming a first electrode 310, a dielectric substance 320, and a second electrode 330 under a supporting body 350 are connected to the second wiring layers 120. A die attaching tape 400 is arranged under the capacitor component 300. Also, a second interlayer insulating layer 220 is formed on the capacitor component 300 such that the capacitor component 300 is embedded in this second interlayer insulating layer 220.
Also, third wiring layers 140 connected to the second wiring layers 120 via second via holes VH2 formed in the second interlayer insulating layer 220 are formed on the second interlayer insulating layer 220. A solder resist 500 to the connection portions of which opening portions 500x are provided is formed on the third wiring layers 140. Also, bumps 600a of a semiconductor chip 600 are flip-chip connected to connection portions of the third wiring layers 140.
In Patent Literature 1 (Patent Application Publication (KOKAI) 2001-291637), it is set forth that the spherical capacitor constructed such that the first electrode, the dielectric substance, and the second electrode are stacked on a surface of the spherical core and electrode portions of the first electrode are exposed is provided and connected to the electric wire circuit of the wiring substrate.
In Patent Literature 2 (Patent Application Publication (KOKAI) 2006-120696), it is set forth that the capacitor being constructed by the internal electrode formed of the porous metal layer in which a plurality of bubbles are provided from an inner surface to an outer surface, the dielectric layer provided onto inner surfaces of the bubbles and an outer surface of the internal electrode, and the external electrode formed to contact the dielectric layer is inserted into the circuit substrate, and then the semiconductor chip is mounted on such circuit substrate.
In the above electronic component device shown in FIG. 1 in the prior art, the capacitor component 300 on the lower side of which the connection terminals 340 are flat-mounted on the wiring substrate. In order to connect the semiconductor chip 600 to the capacitor component 300, the connection terminals 340 of the capacitor component 300 must be lifted up to the overlying third wiring layers 140 via the second via holes VH2 after the connection terminals 340 of the capacitor component 300 are connected to the second wiring layers 120 so that the capacitor component 300 is buried with the second interlayer insulating layer 220. Therefore, wiring routes from the capacitor component 300 to the semiconductor chip 300 are relatively long.
As a result, a relatively large inductance exists between leads of the semiconductor chip 600 and the capacitor component 300 respectively. In some cases, an effect of the decoupling capacitor cannot be sufficiently achieved.
Also, in the prior art, such problems have arisen that it is difficult to change the wiring routes because positions of the connection terminals of the capacitor component are restricted, and a circuit design is restricted and a margin of design is small because the die attaching tape must be used, and others.
Further, in case the two-terminal type stacked ceramic capacitor having the connection terminals on the side surfaces is built in the wiring substrate, the leading of wirings is required similarly. As a result, the similar problems have arisen.